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Data Communication Methods in LabVIEW
LabVIEW contains many data communication methods, each suited for a certain use case. To ensure you implement the correct data communication method for your application, refer to the overview presented in this topic. For detailed information about a particular data communication method, click the title of the data communication method you want to learn more about.
Data Communication Type:
Dataflow Elements
Buffer Interfaces
Variable Interfaces
Use Case:
Sending data between most block diagram objects.
Sending data between locations when it is important to avoid overwriting or losing any value.
Storing a readily-accessible value in memory where the latest value is of primary interest. Use carefully to avoid race conditions .
Examples:
Passing data from a VI output to a VI input.
Acquiring a waveform; sending a message or command; streaming an image.
Monitoring the current temperature; monitoring the system state.
Categories:
��Wire ��Shift register ��Feedback Node ��Channel Wire
Intra-Target or PC
��Queue ��RT FIFO ��User events ��Asynchronous Message Communication (AMC) Reference Library
Networked
��Network streams ��TCP ��Simple TCP Messaging (STM) Reference Library
Intra-FPGA
��Target-scoped FIFO ��VI-defined FIFO ��DRAM
FPGA to/from Host
��DMA FIFO
FPGA to FPGA
��Peer-to-Peer (P2P) FIFO
Intra-Target or PC
��Local variable ��Global variable ��Functional global variable (FGV) ��Single-process shared variable ��Data value reference ��Current Value Table (CVT)
Networked
��Network-published shared variable ��Programmatic Shared Variable API ��Web services ��UDP
Intra-FPGA
��Global variable ��Memory item ��Register item
FPGA to/from Host
��Read/Write Control ��NI Scan Engine and Variables ��User-defined I/O variable
Dataflow Elements
To take advantage of the dataflow programming environment in LabVIEW, you should use wires, shift registers, feedback nodes, and channel wires as the primary data communication methods in your application.
Method
Attributes
Wire
Primary data transfer between block diagram objects
Shift register
Primary data transfer between loop iterations
Feedback Node
Primary data transfer between iterations of code (does not require a loop)
Channel Wire
Primary data transfer for asynchronous communication between parallel sections of code
Buffer Interfaces
Use buffer interfaces when you must send data from one location to another and you do not want to overwrite or lose any value. A buffer interface is often represented as a FIFO (first-in, first-out) single or multi-element buffer where one or more writers add data onto one end of the buffer and a reader retrieves data from the other end.
Intra-Target or PC
Method
Attributes
Queue
Flexible sizing and access options
Non-deterministic
RT FIFO (Real-Time Module)
Deterministic
Polling mode (default) handles read/write wait times deterministically, but creates high CPU overhead
Blocking mode optimizes CPU utilization during read/write wait times, but does not handle the operations deterministically
Less flexible than queues because of fixed size and limited access options
User events
Asynchronous Messaging Communication (AMC) Library (Available at ni.com )
Message communication within a process and between processes
Greater ease of use compared to queues when designing a messaging framework
Includes the Queued Message Handler (QMH) templateNote: This is community content subject to the Sample Code License Terms available at ni.com/samplecodelicense
Networked
Method
Attributes
Network streams
1:1 communication
Simpler to implement than TCP
Automatically handle disconnections and reconnections
Unidirectional
Available only for Windows and Real-Time systems
TCP
Broad functionality for applications that require network communication to devices without network streams support
Low-level protocol introduces implementation complexity
Simple TCP Messaging (STM) Reference Library (Available at ni.com )
Message wrapper around low-level TCP functions
Used to implement 1:N, single server to multiple client communicationNote: This is community content subject to the Sample Code License Terms available at ni.com/samplecodelicense
Intra-FPGA
Method
Attributes
Target-scoped FIFO (FPGA Module)
VI-defined FIFO (FPGA Module)
Implementation options specify the type of storage the FIFO uses: Flip-flops, Look-Up Table, or Block Memory
Avoids resource conflicts in reentrant subVIs by replicating the resource for each instance
Facilitates reusing code for VIs in multiple projects
Not viewable or customizable from the Project Explorer window
DRAM (FPGA Module)
Interface with dynamic random access memory (DRAM) using a memory item or CLIP interface
Provides a large amount of buffered memory space compared to Target-scoped and VI-defined FIFOs
Nondeterministic access latency
Not available on all targets
FPGA to/from Host
Method
Attributes
DMA FIFO (FPGA Module)
FPGA to FPGA
Variable Interfaces
Use variable interfaces when you must store a value in memory that readers and writers can access with minimal or no flow control. Note that you should use variables in cases where the latest value is of primary interest and it is acceptable to overwrite previous values. Use carefully to avoid race conditions .
Intra-Target or PC
Method
Attributes
Local variable
Stores data accessible from a single VI
Global variable
Stores data accessible from multiple VIs in the same LabVIEW application instance
Functional global variable (FGV)
VI that uses uninitialized shift registers to store global data
Capable of implementing simple global variables, as well as more complex data structures, such as stacks or queue buffers
Helps prevent race conditions by defining specific operations that calling code can perform on the variable
Single-process shared variable
Data value reference
Stores large data sets
Helps manage memory and avoid data copies
Current Value Table (CVT) (Available at ni.com )
Common data repository for variables in applications with separate components
Uses less computing resources than shared variables by centralizing I/O operationsNote: This is community content subject to the Sample Code License Terms available at ni.com/samplecodelicense
Networked
Method
Attributes
Network-published shared variable
Deterministic option available
Ideal for monitoring values
Stores values in a network data server (Shared Variable Engine)
Built-in connection manager for 1:N and N:1 network configurations
Programmatic Shared Variable API
Improves design scalability by providing dynamic access to variables instead of static node-based binding
Access multiple variables with a single variable API function
Access network-published I/O variables
Web services
Network data communication using standard HTTP protocols
Stream standard MIME data types, such as text, images, and videos
Build and deploy web services using LabVIEW VIs
UDP
Supports single-cast (1:1) and multicast (1:N) for low-level communication among processes on devices
Higher performance than TCP in applications that do not require lossless data transfer
Low-level protocol introduces implementation complexity
Does not guarantee clients receive data
Intra-FPGA
Method
Attributes
Global variable
Stores data accessible from multiple VIs in the same LabVIEW application instance
Memory item (FPGA Module)
Capable of storing values as multiple data points
Implementation options specify the type of storage the memory item uses: Block Memory, Look-Up Table, or DRAM
Target-scoped (configured in the project) and VI-defined (configured in a VI for reentrant use) options
Register item (FPGA Module)
Capable of posting a status every clock cycle
Target-scoped (configured in the project) and VI-defined (configured in a VI for reentrant use) options
Consume fewer FPGA resources than FIFOs
FPGA to/from Host
Method
Attributes
Read/Write Control (FPGA Module)
Reads or writes to a control or indicator in the top-level FPGA VI on the FPGA target.
NI Scan Engine and Variables (FPGA Module + NI Scan Engine support on your target)
Simple, periodic communication of FPGA I/O data to/from an RT host
Reduces code required to transfer I/O data between an FPGA target and RT host
User-defined I/O variable (FPGA Module)
Send user-defined data when using the Scan Engine in Hybrid mode
Data transfer between an FPGA VI and LabVIEW RT host VI
Transfer custom FPGA-processed I/O data