Owning Palette: Execution Control Express VIs and Structures
Requires: DSP Module, FPGA Module, or Real-Time Module
Delays for a certain time interval before the output data dependence becomes valid.
(Real-Time Module) The Wait Express VI waits the specified count time and then returns the value of a free running counter. When the Wait Express VI executes, it sleeps and blocks the execution of other code running in the same thread.
Dialog Box Options |
Block Diagram Inputs |
Block Diagram Outputs |
Add to the block diagram | Find on the palette |
Parameter | Description | ||
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Counter Units | Unit of time the VI uses for the counter.
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Size of Internal Counter | Specifies the maximum time a timer can track. To save space on the FPGA, use the smallest Size of Internal Counter possible for the FPGA VI. |
Parameter | Description |
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Count | The time spent in the component. |
Parameter | Description |
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Tick Count | Returns the value of a free running counter at the time the VI wakes up. A free running counter rolls over when the counter reaches the maximum of Size of Internal Counter specified in the configuration dialog box. |
If you do not have the FPGA, Real-Time, or DSP modules, you can use the Wait (ms) function instead.
Note (Real-Time Module, Windows) When the Wait Express VI runs inside a timed structure or a VI set to time-critical priority, it blocks the execution of all other code in the same timed structure or VI because timed structures and time-critical VIs are single-threaded. In all other cases, the Wait Express VI sleeps while other code in the calling VI runs in parallel on separate threads. |