Configure Condition Dialog Box

Requires: Base Development System

Right-click a Conditional Disable structure and select Add Subdiagram After, Add Subdiagram Before, Duplicate Subdiagram, or Edit Condition For This Subdiagram from the shortcut menu to display this dialog box.

Use this dialog box to configure when a subdiagram executes.

This dialog box includes the following components:

• Expression—Specifies a set of conditional statements that LabVIEW evaluates to determine the active subdiagram of the structure. The expression includes the following components:
  • Symbol(s)—Lists all available symbols.
    
    

    Symbol	Description
    CPU	Specifies the processor on which the subdiagram executes. The VI must be in a LabVIEW project to access this symbol.
    DeviceCode	Specifies the target-specific product identifier code in hexadecimal format.
    FPGA_EXECUTION_MODE	Specifies to execute a different subdiagram within an FPGA VI depending on whether the execution mode is set to: FPGA target Simulation (Simulated I/O) Simulation (Real I/O) Third-Party Simulation The VI must be under an FPGA target in a LabVIEW project to access this symbol.
    FPGA_TARGET_FAMILY	Specifies to execute a different subdiagram within an FPGA VI depending on the FPGA family, such as Virtex-II or Virtex-5. The VI must be under an FPGA target in a LabVIEW project to access this symbol.
    FPGA_TARGET_CLASS	Specifies the target class of the FPGA target. For example, the FPGA_TARGET_CLASS of the NI PXIe-7965R is PXIE-7965R and the FPGA_TARGET_FAMILY is VIRTEX5.
    OS	Specifies the OS on which the subdiagram executes. The VI must be in a LabVIEW project to access this symbol.
    RUN_TIME_ENGINE	Specifies whether the subdiagram executes when you create a LabVIEW stand-alone application or shared library that uses the LabVIEW Run-Time Engine.
    TARGET_BITNESS	Specifies the bitness of the instance of LabVIEW or the LabVIEW Run-time Engine that executes the subdiagram.
    TARGET_TYPE	Specifies on which platforms or which targets the subdiagram executes.
    <Custom Symbol>	You can define custom symbols in the Conditional Disable Symbols page to add symbols to this list. You also can enter a symbol in the Symbol(s) pull-down menu. If the symbol you enter is not defined in the Conditional Disable Symbols page, an asterisk appears next to the symbol. Both symbols and their valid values are case-sensitive strings.

  • ==/!=—Lists the comparison operators available for use within the expression. Valid comparisons are ==, which specifies that the symbol is equal to the value, and !=, which specifies that the symbol is not equal to the value.
  • Value(s)—Specifies the value of the symbol you select. Value(s) is a case-sensitive string, so you must enter one of the following valid values exactly as it appears below.
    
    

    Symbol	Valid Values
    CPU	PowerPC x86 null
    DeviceCode	Refer to the Conditional Disable Symbols page of the RT Target Properties dialog box to find the value defined by the target.
    FPGA_EXECUTION_MODE	FPGA_TARGET DEV_COMPUTER_SIM_IO DEV_COMPUTER_REAL_IO THIRD_PARTY_SIMULATION
    FPGA_TARGET_FAMILY	VIRTEX2 VIRTEX5 VIRTEX6 SPARTAN3 SPARTAN6 ZYNQ KINTEX7
    FPGA_TARGET_CLASS	Refer to the Conditional Disable Symbols page of the FPGA Target Properties dialog box to find the value defined by the target.
    OS	Linux Mac null PharLap VxWorks Win
    RUN_TIME_ENGINE	True False
    TARGET_BITNESS	32 64
    TARGET_TYPE	Windows FPGA Embedded RT Mac Unix PocketPC DSP

• Make Default?—Specifies if the current subdiagram is the default subdiagram.